64th IEDM takes shape

• Interconnects to Enable Continued Technology Scaling – BEOL copper (Cu) interconnects are close to end-of-life as a manufacturing technology, while the increasing complexity of MEOL processes requires novel materials. Also, the end of the Cu roadmap will coincide with significant changes in the dominant transistor architecture, and therefore the interaction between transistor architecture and interconnect will drive future interconnect development. This session provides a holistic perspective of interconnect scaling challenges and solutions. It will address the drivers of future interconnect architectures, the process options likely to be implemented in manufacturing, and how they will be tuned to ensure circuit reliability is maintained. 
• Interconnect Design and Technology Optimization for Conventional and Exotic Nanoscale Devices: A Physical Design Perspective, A. Naeemi, Georgia Tech 
• Mechanisms of Electromigration Damage in Cu Interconnects, C. K. Hu, IBM 
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• Interconnect Metals Beyond Copper: Reliability Challenges and Opportunities, K. Croes, Imec 
• Microstructure Evolution and Effect on Resistivity for Cu Nano-interconnects and Beyond, Paul Ho, UT Austin 
• Integrating Graphene into Future Generations of BEOL Interconnects, H.-S. Philip Wong, Stanford 
• Interconnect Trends for Single Digit Nodes, Mehul Naik, Applied Materials 

90-Minute Tutorials – Saturday, Dec. 1

A series of 90-minute tutorial sessions on emerging technologies will be presented by experts in the fields, bridging the gap between textbook-level knowledge and leading-edge current research.

• Reliability Challenges in Advanced Technologies, Ryan Lu, TSMC 
• STT-MRAM Design and Device Requirements, Shinichiro Shiratake, Toshiba Memory 
• Quantum Computing Primer, Mark B. Ritter, IBM 
• Power Transistors in Integrated BCD Technologies,  Hal Edwards, Texas Instruments 
• Design-Technology Co-optimization at RF and mmWave, Bertand Parvais, IMEC 
• Emerging Device Technologies for Neuromorphic Computing, Damien Querlioz, CNRS 

Short Courses – Sunday, Dec. 2

Full-day Short Courses will be held, offering the opportunity to learn about important areas and developments, and to network with experts from around the world.

• It’s All About Memory, Not Logic!, organized by Nirmal Ramaswamy, Micron 
• DRAM: Its Challenging History and Future, Dong Soo Woo, Samsung 
• 3D Flash Memories: Overview of Cell Structures, Operations and Scaling Challenges, Makoto Fujiwara, Toshiba Memory Corporation. 
• Emerging Memories Including Cross-Point, Opportunities and Challenges, Kiran Pangal, Intel 
• Memory Reliability, Qualification and their Relation to System-Level Reliability Strategies, Todd Marquart, Micron 
• Packaging Technology for High Bandwidth Memory, Nick (Namseog) Kim, SK Hynix 
• Processing in Memory (PIM): Performance and Thermal Challenges and Opportunities, Mircea Stan, UVA 

• Scaling Survival Guide in the More-than-Moore Era, organized by Jin Cai, TSMC 

• Extreme-UV Lithography – Principles, Present Status and Outlook, Tony Yen, ASML 
• MOSFET Scaling Knobs (GAA, NCFET…) and Future Alternatives, Witek Maszara, Globalfoundries 
• Overcoming Variation Challenges, Sivakumar Mudanai, Intel 
• Embedded Memory: Present Status and Emerging Architecture and Technology for Future Applications,Eric Wang, TSMC 
• 3D Integration for Density and Functionality, Julien Ryckaert, Imec 
• Advanced Packaging: the Next Frontier for Moore’s “Law,” Subramanian Iyer, UCLA 

Plenary Presentations – Monday, Dec. 3

• Future Computing Hardware for AI, Jeffery Welser, Vice President, IBM Research-Almaden 
• “4th Industrial Revolution and Foundry: Challenges and Opportunities,” Eun Seung Jung, President of Foundry Business, Samsung Electronics 
• The Status, Challenges and Opportunities of 5G, Prof. Gerhard P. Fettweis, TU Dresden 

Evening Panel Session – Tuesday evening, Dec. 4

• EUV: Too Little, Too Late, Too Expensive or the Ultimate Cure-All?, organized by Sanjay Natarajan, Senior VP of Applied Materials. Much progress has been made in EUV patterning technology, and yet manufacturing throughput, masks, pellicles and resists still persist as problems today. The complexity of reliably transferring features at the 7nm node and below using quadruple patterning and 193nm immersion is affecting yield, affecting the cost-per-gate reduction and slowing down Moore’s Law. The industry eagerly awaits EUV, but is it too little, too late and too expensive, or is it the ultimate panacea? A team of world-renowned experts from the leading logic and memory IDMs, foundries and fabless companies will vigorously debate the issue. 

Luncheon – Wednesday, Dec. 5

The speakers are yet to be determined, but IEDM will have a new lunch event this year that features industry leaders engaging the audience on the state of the industry, and on careers in device and VLSI technology.

Vendor Exhibition/Poster Sessions

• A vendor exhibition will be held once again, with special exhibit events in the evenings. 
• This year two poster sessions will be held, one on MRAM technology organized by the IEEE Magnetics Society, the other a student research showcase hosted by the Semiconductor Research Corporation