Imec makes Ge GAA FET.
- Auteur:Ella Cai
- Relâchez le:2017-06-12
Imec has demo-ed scaled strained germanium p-channel Gate-All-Around (GAA) FETs with a sub-10nm diameter.
High-mobility materials such as germanium and III-V have been considered as potential solutions for deeply scaled devices, due to their higher intrinsic carrier mobility.
However, these materials have a larger permittivity and a smaller bandgap than silicon, making it more difficult to apply the necessary electrostatic control at scaled gate lengths.
To mitigate this issue, new device architectures with better electrostatics are necessary. Imec’s results bring significant improvements for both strained germanium p-channel FinFET and gate all around (GAA) devices.
Imec’s Nadine Collaert says that her team “adapted the process flow of our previously published 14/16nm-node strained germanium p-finFETs to study the benefit of strained germanium GAA p-FETs at short gate lengths and sub-10nm diameter.”
The team managed to process GAA p-FETs with the shortest gate lengths (LG=40nm) and smallest nanowire diameter (d=9nm) reported to date. At these shortest gate lengths, the devices maintain excellent electrostatic control with a drain-induced barrier lowering of 30mV/V and a sub-threshold slope of 79mV/dec.
High-mobility materials such as germanium and III-V have been considered as potential solutions for deeply scaled devices, due to their higher intrinsic carrier mobility.
However, these materials have a larger permittivity and a smaller bandgap than silicon, making it more difficult to apply the necessary electrostatic control at scaled gate lengths.
To mitigate this issue, new device architectures with better electrostatics are necessary. Imec’s results bring significant improvements for both strained germanium p-channel FinFET and gate all around (GAA) devices.
Imec’s Nadine Collaert says that her team “adapted the process flow of our previously published 14/16nm-node strained germanium p-finFETs to study the benefit of strained germanium GAA p-FETs at short gate lengths and sub-10nm diameter.”
The team managed to process GAA p-FETs with the shortest gate lengths (LG=40nm) and smallest nanowire diameter (d=9nm) reported to date. At these shortest gate lengths, the devices maintain excellent electrostatic control with a drain-induced barrier lowering of 30mV/V and a sub-threshold slope of 79mV/dec.
