Samsung ramping 90-layer 256Gb TLC NAND with Toggle DDR 4.0 interface
- Auteur:Ella Cai
- Relâchez le:2018-07-10
Samsung has started the ramp of 90-layer 256Gb 3D TLC NAND with the ‘Toggle DDR 4.0’ interface which transfers data between storage and memory at 1.4Gbps which is a 40% increase from its 64-layer predecessor.
The energy efficiency of Samsung’s new V-NAND remains comparable to that of the 64-layer chip, primarily because the operating voltage has been reduced from 1.8V to 1.2V.
The memory has a write speed of 500μs which represents about a 30% improvement over the write speed of the previous generation, while the response time to read-signals has been significantly reduced to 50μs.
The chip has more than 90 layers of 3D charge trap flash (CTF) cells, the largest amount in the industry, stacked in a pyramid structure with the channel holes vertically drilled throughout.
These channel holes contain more than 85 billion CTF cells that can store three bits of data each
Thanks to enhancements in the V-NAND’s atomic layer deposition process, manufacturing productivity has also increased by more than 30%.
The technique allows the height of each cell layer to be reduced by 20%, prevents crosstalk between cells and increases the efficiency of the chip’s data processing.
“We are preparing to introduce 1-terabit (Tb) and QLC (quad-level cell) offerings to our V-NAND line-up” says Samsung’s Kye Hyun Kyung.
The energy efficiency of Samsung’s new V-NAND remains comparable to that of the 64-layer chip, primarily because the operating voltage has been reduced from 1.8V to 1.2V.
The memory has a write speed of 500μs which represents about a 30% improvement over the write speed of the previous generation, while the response time to read-signals has been significantly reduced to 50μs.
The chip has more than 90 layers of 3D charge trap flash (CTF) cells, the largest amount in the industry, stacked in a pyramid structure with the channel holes vertically drilled throughout.
These channel holes contain more than 85 billion CTF cells that can store three bits of data each
Thanks to enhancements in the V-NAND’s atomic layer deposition process, manufacturing productivity has also increased by more than 30%.
The technique allows the height of each cell layer to be reduced by 20%, prevents crosstalk between cells and increases the efficiency of the chip’s data processing.
“We are preparing to introduce 1-terabit (Tb) and QLC (quad-level cell) offerings to our V-NAND line-up” says Samsung’s Kye Hyun Kyung.
