Toshiba prototypes 96-layer 1.3Tbit NAND
- Auteur:Ella Cai
- Relâchez le:2018-07-23
Toshiba has developed a prototype 96-layer NAND memory chip using 3D flash quad level cell (QLC) technology.
The IC achieves the industry’s maximum capacity of 1.33 terabits for a single chip.
This also realises an unparalleled capacity of 2.66 terabytes in a single package by utilising a 16-chip stacked architecture.
The huge volumes of data generated by mobile terminals and the like continue to increase with the spread of SNS and the progress in IoT and the demand for analysing and utilising that data in real time is expected to increase dramatically.
This will require even faster HDDs and larger capacity storage and such QLC-based products, using the 96-layer process, will contribute to the solution.
Toshiba Memory will start to deliver samples to SSD and SSD controller manufacturers for evaluation from the beginning of September and expects to start mass production in 2019.
The IC achieves the industry’s maximum capacity of 1.33 terabits for a single chip.
This also realises an unparalleled capacity of 2.66 terabytes in a single package by utilising a 16-chip stacked architecture.
The huge volumes of data generated by mobile terminals and the like continue to increase with the spread of SNS and the progress in IoT and the demand for analysing and utilising that data in real time is expected to increase dramatically.
This will require even faster HDDs and larger capacity storage and such QLC-based products, using the 96-layer process, will contribute to the solution.
Toshiba Memory will start to deliver samples to SSD and SSD controller manufacturers for evaluation from the beginning of September and expects to start mass production in 2019.
