Hitachi develops TED-MOS
- Autore:Ella Cai
- Rilasciare il:2018-09-17
Hitachi has developed a SiC-based ‘TED-MOS’ (Trench-Etched-Double-Diffused MOS) device using a fin-structured trench MOSFET based on the conventional DMOS-FET.
An energy saving of 50% over a DMOS-FET was confirmed as the structure reduces the electric field strength, an index of durability, by 40% and resistance by 25% compared to a DMOS-FET.
Hitachi intends to apply this device in motor drive inverters which are a core component of EVs to increase energy efficiency.
An issue with SiC power semiconductors is that the resistance varies greatly depending on the crystal plane.
Although trench SiC MOSFET has been proposed as a means to facilitate the flow of electric current on the crystal plane at a lower resistance in comparison to the conventional DMOS-FET structure, as electric fields easily concentrate at the edges of the trench on the base plane, it was difficult to simultaneously achieve high durability.
To address this challenge, Hitachi developed an original fin-structure trench DMOS-FET “TED-MOS” that achieved both a reduction in resistance with the smaller trench pitch and high durability with lower electric fields for industrial applications at high voltage (3.3 kV).
This time, Hitachi has enhanced the “TED-MOS” for EV inverters as they require higher current density at a lower voltage (1.2 kV).
The “field relaxation layer (FRL)” was developed to reduce the electric field strength extensively, where the PN junction to relax the applied voltage forms in the center of the device structure. In addition, the “current spreading layer (CSL)” was developed to reduce the resistance in the n-JFET region, which serves to form the electric current path connecting the sides of the fin-like trenches as low-resistance crystal planes and the n-JFET region.
As a result, “TED-MOS” simultaneously achieves both a smaller electric field strength and lower resistance in SiC power semiconductors.
An energy saving of 50% over a DMOS-FET was confirmed as the structure reduces the electric field strength, an index of durability, by 40% and resistance by 25% compared to a DMOS-FET.
Hitachi intends to apply this device in motor drive inverters which are a core component of EVs to increase energy efficiency.
An issue with SiC power semiconductors is that the resistance varies greatly depending on the crystal plane.
Although trench SiC MOSFET has been proposed as a means to facilitate the flow of electric current on the crystal plane at a lower resistance in comparison to the conventional DMOS-FET structure, as electric fields easily concentrate at the edges of the trench on the base plane, it was difficult to simultaneously achieve high durability.
To address this challenge, Hitachi developed an original fin-structure trench DMOS-FET “TED-MOS” that achieved both a reduction in resistance with the smaller trench pitch and high durability with lower electric fields for industrial applications at high voltage (3.3 kV).
This time, Hitachi has enhanced the “TED-MOS” for EV inverters as they require higher current density at a lower voltage (1.2 kV).
The “field relaxation layer (FRL)” was developed to reduce the electric field strength extensively, where the PN junction to relax the applied voltage forms in the center of the device structure. In addition, the “current spreading layer (CSL)” was developed to reduce the resistance in the n-JFET region, which serves to form the electric current path connecting the sides of the fin-like trenches as low-resistance crystal planes and the n-JFET region.
As a result, “TED-MOS” simultaneously achieves both a smaller electric field strength and lower resistance in SiC power semiconductors.
