Cadence takes chip verification in cloud to new level
- 著者:Ella Cai
- 公開：:2017-04-13
Cadence Design Systems is offering semiconductor IC design verification which makes use of parallel computing resources in the cloud.
Called Pegasus, the verification tool has the capability to offer fast design rule check (DRC) performance on hundreds of CPUs while also reducing turnaround time from days to hours versus the previous-generation Cadence verification tool.
Print“Engineers have experienced increasing DRC complexity at advanced nodes, and current DRC solutions can’t support the turnaround requirements needed to ensure that design schedules are met,” said Dr. Anirudh Devgan, general manager of the system and verification group at Cadence.
The tool makes use of cloud computing which means that data processing capability is scalable and Cadence says it has been demonstrated on up to 960 CPUs.
“The solution’s data flow architecture enables customers to optimise CPU usage, regardless of machine configurations and physical location, providing maximum flexibility to run on a wide range of hardware, achieving the fastest DRC signoff,” said Cadence.
According to Devgan, the use of native cloud-ready processing provides an elastic computing environment, which “can enable our customers to complete full-chip signoff DRC on advanced-node designs in a matter of hours, speeding time to market.”
The Pegasus Verification tool suite includes a full flow from synthesis through implementation and signoff.
Called Pegasus, the verification tool has the capability to offer fast design rule check (DRC) performance on hundreds of CPUs while also reducing turnaround time from days to hours versus the previous-generation Cadence verification tool.
Print“Engineers have experienced increasing DRC complexity at advanced nodes, and current DRC solutions can’t support the turnaround requirements needed to ensure that design schedules are met,” said Dr. Anirudh Devgan, general manager of the system and verification group at Cadence.
The tool makes use of cloud computing which means that data processing capability is scalable and Cadence says it has been demonstrated on up to 960 CPUs.
“The solution’s data flow architecture enables customers to optimise CPU usage, regardless of machine configurations and physical location, providing maximum flexibility to run on a wide range of hardware, achieving the fastest DRC signoff,” said Cadence.
According to Devgan, the use of native cloud-ready processing provides an elastic computing environment, which “can enable our customers to complete full-chip signoff DRC on advanced-node designs in a matter of hours, speeding time to market.”
The Pegasus Verification tool suite includes a full flow from synthesis through implementation and signoff.
