Toshiba sampling 3D NAND with TSVs
- 著者:Ella Cai
- 公開：:2017-07-12
Toshiba is sampling a 3D NAND TLC memory which uses TSVs.
Devices with TSV technology have vertical electrodes and vias that pass through silicon dies to provide connections, an architecture that realizes high speed data input and output while reducing power consumption.
Combining a 48-layer 3D flash process and TSV technology increases product programming bandwidth while achieving low power consumption.
The power efficiency of a single package is approximately twice that of the same generation BiCS FLASH memory fabricated with wire-bonding technology.
TSV BiCS FLASH enables a 1TB device with a 16-die stacked architecture in a single package.
Toshiba will commercialise BiCS FLASH with TSV technology to address storage applications requiring low latency, high bandwidth and high IOPS/Watt, including high-end enterprise SSDs.
Shipments of prototypes for development purposes started in June, and product samples are scheduled for release in the second half of 2017.
Devices with TSV technology have vertical electrodes and vias that pass through silicon dies to provide connections, an architecture that realizes high speed data input and output while reducing power consumption.
Combining a 48-layer 3D flash process and TSV technology increases product programming bandwidth while achieving low power consumption.
The power efficiency of a single package is approximately twice that of the same generation BiCS FLASH memory fabricated with wire-bonding technology.
TSV BiCS FLASH enables a 1TB device with a 16-die stacked architecture in a single package.
Toshiba will commercialise BiCS FLASH with TSV technology to address storage applications requiring low latency, high bandwidth and high IOPS/Watt, including high-end enterprise SSDs.
