UltraSoC to offer processor trace support for RISC-V
- 著者:Ella Cai
- 公開：:2017-06-20
In Q4, the embedded analytics specialist UltraSoC, will offer processor trace support for products based on the open source RISC-V architecture.
The company has developed a specification for processor trace that will be offered for adoption by the RISC-V Foundation as part of the open source specification.
Five core vendors have already announced their support for the new trace specification, which is a key function for software developers using any processor.
RISC-V is an open source instruction set architecture, initially developed by UC Berkeley but now being more widely adopted. Processor trace functionality allows the behavior of a programme to be viewed instruction-by-instruction.
“RISC-V is a great architecture: but an architecture is not enough,” says UltraSoC CEO Rupert Bainespictured), “customers need the whole ecosystem – an ecosystem that puts designers in control and empowers innovation. UltraSoC is aiming to play a major role in that with our debugging and development IP, and processor trace for RISC-V is a significant supporting pillar in that effort.”
UltraSoC is working with major RISC-V core vendors including Andes, Codasip, Roa Logic, SiFive and Syntacore, with the intention of submitting a proposed processor trace format to the RISC-V Foundation later in 2017 as the basis of the open source standard implementation.
has a dozen high-profile licensees, including HiSilicon (Huawei), Imagination Technologies, Movidius (now Intel), and Microsemi. UltraSoC’s partners include Andes, ARM, Baysand, Cadence/Tensilica, CEVA, Codasip, Lauterbach, MIPS, Roa Logic, Syntacore and Teledyne LeCroy.
The company has developed a specification for processor trace that will be offered for adoption by the RISC-V Foundation as part of the open source specification.
Five core vendors have already announced their support for the new trace specification, which is a key function for software developers using any processor.
RISC-V is an open source instruction set architecture, initially developed by UC Berkeley but now being more widely adopted. Processor trace functionality allows the behavior of a programme to be viewed instruction-by-instruction.
“RISC-V is a great architecture: but an architecture is not enough,” says UltraSoC CEO Rupert Bainespictured), “customers need the whole ecosystem – an ecosystem that puts designers in control and empowers innovation. UltraSoC is aiming to play a major role in that with our debugging and development IP, and processor trace for RISC-V is a significant supporting pillar in that effort.”
UltraSoC is working with major RISC-V core vendors including Andes, Codasip, Roa Logic, SiFive and Syntacore, with the intention of submitting a proposed processor trace format to the RISC-V Foundation later in 2017 as the basis of the open source standard implementation.
has a dozen high-profile licensees, including HiSilicon (Huawei), Imagination Technologies, Movidius (now Intel), and Microsemi. UltraSoC’s partners include Andes, ARM, Baysand, Cadence/Tensilica, CEVA, Codasip, Lauterbach, MIPS, Roa Logic, Syntacore and Teledyne LeCroy.
