Leti claims 3D chip breakthrough on 300mm wafers
- 저자:Ella Cai
- 에 출시:2017-11-15
Leti, an institute of CEA Tech, has announced the world’s first successful 300mm wafer-to-wafer direct hybrid bonding with pitch dimension connections as small as 1µm and copper pads as small as 500nm.
This was achieved in partnership with EV Group, a supplier of wafer bonding and lithography equipment.
“To our knowledge, this is the first reported demonstration of sub-1.5µm pitch copper hybrid bonding feasibility,” said Frank Fournel, head of bonding process engineering at Leti.
The copper/oxide hybrid bonding process is used in the fabrication of 3D high-density ICs.
Wafer bonding for 3D device stacking
Vertical stacking of semiconductor devices has become an increasingly viable approach to enabling continuous improvements in device density and performance.
Wafer-to-wafer bonding is a crucial process step to enable 3D stacked devices. However, tight alignment and overlay accuracy between the wafers is required to achieve good electrical contact between the interconnected device on the bonded wafers, as well as to minimise the interconnect area at the bond interface so that more space can be made available on the wafer for producing devices.
The constant reduction in pitches that are needed to support component roadmaps is fuelling tighter wafer-to-wafer bonding specifications with each new product generation.
In the Leti demonstration, the top and bottom 300mm wafers were directly bonded in EVG’s GEMINI FB XT production fusion bonding system.
The system achieved overlay alignment accuracy to within 195nm (3-sigma) overall, with mean alignment results well centred below 15nm.
Post-bake
Post-bake acoustic microscopy scans of the full 300-mm bonded wafer stack as well as specific dies confirmed a defect-free bonding interface for pitches ranging from 1µm to 4µm with optimum copper density.
“3D integration holds the promise for increased device density and bandwidth as well as lower power consumption for a variety of applications, from next-generation CMOS image sensors and MEMS to high-performance computing,” said Markus Wimplinger, corporate technology development and IP director at EV Group.
This demonstration was described in a paper titled: “1 µm Pitch Direct Hybrid Bonding with <300nm Wafer-to-wafer Overlay Accuracy,” which was presented at the 2017 IEEE S3S Conference.
This was achieved in partnership with EV Group, a supplier of wafer bonding and lithography equipment.
“To our knowledge, this is the first reported demonstration of sub-1.5µm pitch copper hybrid bonding feasibility,” said Frank Fournel, head of bonding process engineering at Leti.
The copper/oxide hybrid bonding process is used in the fabrication of 3D high-density ICs.
Wafer bonding for 3D device stacking
Vertical stacking of semiconductor devices has become an increasingly viable approach to enabling continuous improvements in device density and performance.
Wafer-to-wafer bonding is a crucial process step to enable 3D stacked devices. However, tight alignment and overlay accuracy between the wafers is required to achieve good electrical contact between the interconnected device on the bonded wafers, as well as to minimise the interconnect area at the bond interface so that more space can be made available on the wafer for producing devices.
The constant reduction in pitches that are needed to support component roadmaps is fuelling tighter wafer-to-wafer bonding specifications with each new product generation.
In the Leti demonstration, the top and bottom 300mm wafers were directly bonded in EVG’s GEMINI FB XT production fusion bonding system.
The system achieved overlay alignment accuracy to within 195nm (3-sigma) overall, with mean alignment results well centred below 15nm.
Post-bake
Post-bake acoustic microscopy scans of the full 300-mm bonded wafer stack as well as specific dies confirmed a defect-free bonding interface for pitches ranging from 1µm to 4µm with optimum copper density.
“3D integration holds the promise for increased device density and bandwidth as well as lower power consumption for a variety of applications, from next-generation CMOS image sensors and MEMS to high-performance computing,” said Markus Wimplinger, corporate technology development and IP director at EV Group.
This demonstration was described in a paper titled: “1 µm Pitch Direct Hybrid Bonding with <300nm Wafer-to-wafer Overlay Accuracy,” which was presented at the 2017 IEEE S3S Conference.
