eFPGA out-growing FPGA at Achronix
- Author:Ella Cai
- Release on:2017-06-09
Achronix expects eFPGA to be delivering half the company’s revenues in 2020.
“It’s our fastest growing product line, Achronix’ future products will focus on acceleration solutions,” Robert Blake, Achronix CEO (pictured) told EW.
Achronix’ three product lines are: eFPGA IP cores called Speedcore, stand-alone FPGA chips called Speedster and two-chip modules containing an SoC and an FPGA acceleration chip which Achronix calls Speedchip.
“For customers wanting the maximum bandwidth and lowest latency, integrating the core on the chip gives the best performance,” said Blake, “if the SoC is a big die and the accelerator chip is big then it’s best to have two die in one package.”
Customers are both systems houses making their own SoCs, and semiconductor companies making ICs for the networking, computing and wireless infrastructure markets which is where acceleration is increasingly needed.
The need comes from the processing requirements of AI, machine learning, Big Data and the rapidly changing algorithms of ADAS, SQL and data centre learning, all of which need programmable hardware accelerators.
Asked why the foundries aren’t taking licences for eFPGA, Blake replied: “”They haven’t realised yet that it’s a critical IP, but it will happen over time.”
FPGA acceleration has been recognised as a useful technology for many years – IBM embedded a Xilinx core in an SoC – but it was only after Intel bought Altera for $16.7 billion in 2015 that a surge in demand for FPGA acceleration has emerged.
Asked why that was, Blake replied: “We were pitching it five years ago but it was only when 16nm came along that it started to become interesting.”
Achronix’ strand-alone Speedster FPGAs are made on Intel’s 22nm process and its Speedcore eFPGA IP is made on TSMC’s 16nmFF process.
Others have also dived into the eFPGA opportunity like Flex Logix, QuickLogic and NanoExplore but some FPGA old-timers like Lattice, Xilinx and Microsemi via its Actel purchase, have stayed out of the eFPGA market and, though one assumes Intel intends to put an eFPGA fabric onto its processors, there has been so sign of it.
Achronix’ ACE design tools have, said Blake “the ability to generate an arbitrarily-sized building block with exactly the functions a customer needs.”
For Achronix there are four ways of generating revenue from its Speedcore business:
Speedcore eFPGA products are fully supported by Achronix’s ACE design tools.
With Speedcore, customers specify the optimal die size, power consumption and resource configuration required for their end application.
Customers define the quantity of look-up-tables (LUTs), embedded memory blocks and DSP blocks.
Additionally customers define the Speedcore aspect ratio, IO port connections and can make tradeoffs between power and performance.
Achronix delivers a GDS II of the Speedcore IP that customers integrate directly into their SoC, and a custom, full-featured version of the ACE design tools that customers use to design, verify and program the functionality of the Speedcore eFPGA.
“Over the years, different companies have talked about eFPGA products, but Achronix Speedcore was the first eFPGA IP to ship to end customers, and it is a game changer” said Blake, “Achronix was the first company to deliver high density FPGAs with embedded system level IP. We are using that same proven methodology to deliver our eFPGA to customers who want to combine all the efficiencies of ASIC design with the flexibility of eFPGA programmable hardware accelerators on the same chip.”
Achronix’ total revenues were slow to grow – $5 million in Q4 2016 but expected to reach $40 million in Q4 with 2017 total revenue of $100 million.
Achronix won’t talk IP margins but says the chip margins are 50/60% and the IP margins are better.
“It’s our fastest growing product line, Achronix’ future products will focus on acceleration solutions,” Robert Blake, Achronix CEO (pictured) told EW.
Achronix’ three product lines are: eFPGA IP cores called Speedcore, stand-alone FPGA chips called Speedster and two-chip modules containing an SoC and an FPGA acceleration chip which Achronix calls Speedchip.
“For customers wanting the maximum bandwidth and lowest latency, integrating the core on the chip gives the best performance,” said Blake, “if the SoC is a big die and the accelerator chip is big then it’s best to have two die in one package.”
Customers are both systems houses making their own SoCs, and semiconductor companies making ICs for the networking, computing and wireless infrastructure markets which is where acceleration is increasingly needed.
The need comes from the processing requirements of AI, machine learning, Big Data and the rapidly changing algorithms of ADAS, SQL and data centre learning, all of which need programmable hardware accelerators.
Asked why the foundries aren’t taking licences for eFPGA, Blake replied: “”They haven’t realised yet that it’s a critical IP, but it will happen over time.”
FPGA acceleration has been recognised as a useful technology for many years – IBM embedded a Xilinx core in an SoC – but it was only after Intel bought Altera for $16.7 billion in 2015 that a surge in demand for FPGA acceleration has emerged.
Asked why that was, Blake replied: “We were pitching it five years ago but it was only when 16nm came along that it started to become interesting.”
Achronix’ strand-alone Speedster FPGAs are made on Intel’s 22nm process and its Speedcore eFPGA IP is made on TSMC’s 16nmFF process.
Others have also dived into the eFPGA opportunity like Flex Logix, QuickLogic and NanoExplore but some FPGA old-timers like Lattice, Xilinx and Microsemi via its Actel purchase, have stayed out of the eFPGA market and, though one assumes Intel intends to put an eFPGA fabric onto its processors, there has been so sign of it.
Achronix’ ACE design tools have, said Blake “the ability to generate an arbitrarily-sized building block with exactly the functions a customer needs.”
For Achronix there are four ways of generating revenue from its Speedcore business:
Speedcore eFPGA products are fully supported by Achronix’s ACE design tools.
With Speedcore, customers specify the optimal die size, power consumption and resource configuration required for their end application.
Customers define the quantity of look-up-tables (LUTs), embedded memory blocks and DSP blocks.
Additionally customers define the Speedcore aspect ratio, IO port connections and can make tradeoffs between power and performance.
Achronix delivers a GDS II of the Speedcore IP that customers integrate directly into their SoC, and a custom, full-featured version of the ACE design tools that customers use to design, verify and program the functionality of the Speedcore eFPGA.
“Over the years, different companies have talked about eFPGA products, but Achronix Speedcore was the first eFPGA IP to ship to end customers, and it is a game changer” said Blake, “Achronix was the first company to deliver high density FPGAs with embedded system level IP. We are using that same proven methodology to deliver our eFPGA to customers who want to combine all the efficiencies of ASIC design with the flexibility of eFPGA programmable hardware accelerators on the same chip.”
Achronix’ total revenues were slow to grow – $5 million in Q4 2016 but expected to reach $40 million in Q4 with 2017 total revenue of $100 million.
Achronix won’t talk IP margins but says the chip margins are 50/60% and the IP margins are better.
