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- Autor:Ella Cai
- Solte em:2017-08-10
EnSilica, the Wokingham IP specialist, has licensed its eSi-RISC processor IP to fabless touch and display chip vendor Solomon Systech of Hong Kong.
The multi-year licensing agreement covers the full range of EnSilica’s 16-bit and 32-bit eSi-RISC processor IP and extends the existing relationship between the two companies to cover multiple projects and multiple architecture implementations.
Solomon Systech will use the IP for several of its smart touch screen controllers and drivers.
EnSilica’s IP is a configurable microprocessor architecture for embedded systems that scales across a range of applications.
With either a 16-bit or 32-bit, five-stage pipelined RISC, load-store architecture which is configurable and implemented in as little as 8k ASIC gates, the RISC IP core has been silicon proven in a variety of ASIC and FPGA technologies.
It is available in a choice of von Neumann or Harvard memory versions and uses industry standard bus architecture (AMBA AXI/AHB/APB) for IP interconnection, mixed 16-bit and 32-bit instructions to deliver code density at low power.
ESi-RISC is implemented as a soft IP core, based on synthesisable Verilog RTL and can be easily ported to a range of ASIC processes and FPGAs. The design is also DFT ready, supporting full scan insertion for all flip flops and memory BIST.
The multi-year licensing agreement covers the full range of EnSilica’s 16-bit and 32-bit eSi-RISC processor IP and extends the existing relationship between the two companies to cover multiple projects and multiple architecture implementations.
Solomon Systech will use the IP for several of its smart touch screen controllers and drivers.
EnSilica’s IP is a configurable microprocessor architecture for embedded systems that scales across a range of applications.
With either a 16-bit or 32-bit, five-stage pipelined RISC, load-store architecture which is configurable and implemented in as little as 8k ASIC gates, the RISC IP core has been silicon proven in a variety of ASIC and FPGA technologies.
It is available in a choice of von Neumann or Harvard memory versions and uses industry standard bus architecture (AMBA AXI/AHB/APB) for IP interconnection, mixed 16-bit and 32-bit instructions to deliver code density at low power.
ESi-RISC is implemented as a soft IP core, based on synthesisable Verilog RTL and can be easily ported to a range of ASIC processes and FPGAs. The design is also DFT ready, supporting full scan insertion for all flip flops and memory BIST.
