Renesas aims at driver-assitance cameras
- Autor:Ella Cai
- Solte em:2017-04-13
Renesas has announced a chip for forward-facing cameras in automated driving and driver assistance systems.
At the same time, it has branded its driver-assist and automated driving activities ‘Autonomy’.
The chip, called ‘R-Car V3M’ is built around an ARM Cortex-A53 processors and is intended to be built into forward facing cameras, directly connected to the image sensor, and providing all object classification processing.
Its output will be identified objects – human, dog, bicycle, for example, plus each object’s calculated position and estimated motion path, Renasas automated driving spokesman Uwe Westmeyer told Electronics Weekly. Processing elsewhere will combine this with radar and lidar-derived data.
On-board are dual 800MHz ARM Cortex-A53 cores, plus dual lockstep 800MHz ARM Cortex-R7 cores – the latter pair (along with hardware distributed through the chip) there to meet ISO26262 functional safety requirements.
Renesas supports several ASIL functional safety levels: R-Car V3M is ASIL-C, while the earlier R-Car M3 and R-Car H3 are ASIL-B, and the RH850/P1X MCU series are ASIL-D.
Renesas ADAS automated drivingForward facing cameras are positioned at the top of the windscreen behind the read-view mirror, said Westmeyer, so they have to be small, and have to be able to operate exposed to direct sunshine. As such, power constraints are tight, ruling out the exclusively use of general-purpose processors to implement the convolutional neural networks and the other algorithms needed for classification.
Instead, Renesas has included two image-processing hardware accelerators: the image recognition engine (IMP-X5-V3M) and the image signal processor (ISP) – one being dedicated number-crunching deep-learned algorithms power efficiently, and the other more flexible, at the expense of a little more power.
“The new R-Car V3M SoC standard, delivers low-power hardware acceleration for vision processing, and is equipped with a built-in image signal processor (ISP), freeing up board space and reducing system manufacturers’ system costs,” said Renesas.
Renesas autonomyAlso on-die are a memory controller for DDR3L-1600, a video encoder, video outputs (4 lanes x 1 channel LVDS, 1 channel digital), video Inputs (4 lanes x 1 channel MIPI-CSI2, 2 channels digital), two channels of CAN-FD interface, Ethernet AVB and 2x FlexRay interfaces.
Westmeyer describes the architecture as “open”, although information needed to access the accelerators and other hardware will only be available to authorised companies within the associated eco-system.
According to him, Tier 1 automotive suppliers are likely to be developing their own driving assistance and automated driving algorithms from scratch, each putting in millions of road km in the process. Tier 1.5 and 2 firms will be working with other companies in the ecosystem for their algorithms.
At the same time, it has branded its driver-assist and automated driving activities ‘Autonomy’.
The chip, called ‘R-Car V3M’ is built around an ARM Cortex-A53 processors and is intended to be built into forward facing cameras, directly connected to the image sensor, and providing all object classification processing.
Its output will be identified objects – human, dog, bicycle, for example, plus each object’s calculated position and estimated motion path, Renasas automated driving spokesman Uwe Westmeyer told Electronics Weekly. Processing elsewhere will combine this with radar and lidar-derived data.
On-board are dual 800MHz ARM Cortex-A53 cores, plus dual lockstep 800MHz ARM Cortex-R7 cores – the latter pair (along with hardware distributed through the chip) there to meet ISO26262 functional safety requirements.
Renesas supports several ASIL functional safety levels: R-Car V3M is ASIL-C, while the earlier R-Car M3 and R-Car H3 are ASIL-B, and the RH850/P1X MCU series are ASIL-D.
Renesas ADAS automated drivingForward facing cameras are positioned at the top of the windscreen behind the read-view mirror, said Westmeyer, so they have to be small, and have to be able to operate exposed to direct sunshine. As such, power constraints are tight, ruling out the exclusively use of general-purpose processors to implement the convolutional neural networks and the other algorithms needed for classification.
Instead, Renesas has included two image-processing hardware accelerators: the image recognition engine (IMP-X5-V3M) and the image signal processor (ISP) – one being dedicated number-crunching deep-learned algorithms power efficiently, and the other more flexible, at the expense of a little more power.
“The new R-Car V3M SoC standard, delivers low-power hardware acceleration for vision processing, and is equipped with a built-in image signal processor (ISP), freeing up board space and reducing system manufacturers’ system costs,” said Renesas.
Renesas autonomyAlso on-die are a memory controller for DDR3L-1600, a video encoder, video outputs (4 lanes x 1 channel LVDS, 1 channel digital), video Inputs (4 lanes x 1 channel MIPI-CSI2, 2 channels digital), two channels of CAN-FD interface, Ethernet AVB and 2x FlexRay interfaces.
Westmeyer describes the architecture as “open”, although information needed to access the accelerators and other hardware will only be available to authorised companies within the associated eco-system.
According to him, Tier 1 automotive suppliers are likely to be developing their own driving assistance and automated driving algorithms from scratch, each putting in millions of road km in the process. Tier 1.5 and 2 firms will be working with other companies in the ecosystem for their algorithms.
