Renesas claims lowest power SRAM
- Autor:Ella Cai
- Solte em:2017-07-04
Renesas claims the lowest standby power for embedded SRAM of 13.7 nW/Mbit with a 1.84 ns read speed with Implementing silicon on thin BOX (SOTB) 65nm circuit technology.
The prototype SRAM achieves simultaneous high-speed readout time of 1.8 ns during active operation, and ultra-low power consumption of 13.7 nW/Mbit in standby mode.
The SRAM takes advantage of the SOTB structure by using dynamic substrate back bias control to achieve low standby-mode power consumption, which is only one-thousandth of the power consumption during normal standby mode.
Renesas’ technology adopts a method in which the power consumption of the embedded SRAM in standby mode is reduced. This enables intermittent operation to be performed frequently without leading to increased power consumption, thereby making it unnecessary to save data to nonvolatile memory, which leads to improved power efficiency.
Previous Renesas efforts related to embedded SRAM include prototype of an embedded SRAM with a 28-nm high-K metal gate (HKMG) structure and a high-performance embedded SRAM with a 16-nm Fin field-effect transistor (FinFET) structure, which both adopt state-of-the-art process technologies.
These embedded SRAM technologies have been adopted in Renesas’ R-Car automotive infotainment system-on-chips (SoCs).
Now, Renesas has developed circuit technology that dynamically controls the substrate bias using the SOTB process technology and enables standby mode leakage current to be reduced to approximately one-thousandth of the power compared to the normal standby mode.
The technology switches dynamically with low power overhead between active operation in which the CPU core performs read and write operations of the embedded SRAM, and the standby mode in which the stored data is retained.
The prototype SRAM achieves simultaneous high-speed readout time of 1.8 ns during active operation, and ultra-low power consumption of 13.7 nW/Mbit in standby mode.
The SRAM takes advantage of the SOTB structure by using dynamic substrate back bias control to achieve low standby-mode power consumption, which is only one-thousandth of the power consumption during normal standby mode.
In systems that frequently iterate the switching between the active- and standby mode, the saving of data to nonvolatile memory and the restart operation becomes a significant overhead. There are even cases where, inversely, this increases power consumption.
Renesas’ technology adopts a method in which the power consumption of the embedded SRAM in standby mode is reduced. This enables intermittent operation to be performed frequently without leading to increased power consumption, thereby making it unnecessary to save data to nonvolatile memory, which leads to improved power efficiency.
Previous Renesas efforts related to embedded SRAM include prototype of an embedded SRAM with a 28-nm high-K metal gate (HKMG) structure and a high-performance embedded SRAM with a 16-nm Fin field-effect transistor (FinFET) structure, which both adopt state-of-the-art process technologies.
These embedded SRAM technologies have been adopted in Renesas’ R-Car automotive infotainment system-on-chips (SoCs).
Now, Renesas has developed circuit technology that dynamically controls the substrate bias using the SOTB process technology and enables standby mode leakage current to be reduced to approximately one-thousandth of the power compared to the normal standby mode.
