Silicon Labs sampling single-chip 4G/Ethernet clocks
- Autor:Ella Cai
- Solte em:2017-09-26
Silicon Labs is sampling a family of multi-channel jitter attenuating clocks for 4.5G and Ethernet-based Common Public Radio Interface (eCPRI) wireless applications.
The Si5381/82/86 clocks use the company’s DSPLL technology to deliver a timing solution that combines 4G/LTE and Ethernet clocking in a single IC.
The clocks eliminate the need for multiple clock devices and voltage-controlled crystal oscillators (VCXOs) in demanding applications including small cells, distributed antenna systems (DAS), -BTS, baseband units (BBU) and fronthaul/backhaul equipment.
Over the next several years, service providers will lay the groundwork for 5G by deploying small cells, pico cells, DAS, µ-BTS and backhaul equipment that complements existing 4G/LTE networks by increasing outdoor network coverage and capacity and improving indoor signal reception.
As carriers transition to Ethernet-based eCPRI fronthaul networks to increase the capacity of fronthaul connections between base band units and remote radio heads, they are also deploying heterogeneous network (HetNet) equipment at the edge of the network where cost, power and size constraints present unique challenges for hardware designers.
The clocks are optimised to provide reference timing for HetNet equipment. Small cells and DAS equipment are “all-in-one” base stations that need reference timing for 4G/LTE transceivers, baseband processing and Ethernet/Wi-Fi connectivity.
The clocks replace a discrete clock IC, VCXO and loop filter components in a compact, single-chip design.
The clocks integrate five MultiSynth fractional clock synthesizers to provide simplified Ethernet and baseband reference timing. This streamlined, single-PLL design provides superior reliability to alternate solutions that rely on multiple PLLs and discrete oscillators.
Baseband units have complex timing requirements requiring multiple independent clock domains for CPRI or links to remote radio heads, Ethernet-based eCPRI for fronthaul networks and general-purpose clocks for local baseband processing.
The clocks support wireless frequencies up to 3 GHz with flexible any-rate DSPLLs optimized for Ethernet and general-purpose timing. Like the Si5386 clock, the Si5381/82 devices require no external VCXOs or crystals.
All PLL components are integrated on-chip in a space-saving 9 mm x 9 mm 64-LGA package. In addition, the clocks support a hitless switching capability that enables system designers to easily switch between different clock inputs and minimize phase transients, ensuring downstream PLLs remain in lock.
The devices are configurable and customizable using Silicon Labs’ flexible ClockBuilder Pro software.
Samples of the Si5381/82/86 wireless clocks are available now, and production quantities are planned to be available in December. Samples ship in two weeks, and production quantities are available in four weeks.
The Si5381/82/86 clocks use the company’s DSPLL technology to deliver a timing solution that combines 4G/LTE and Ethernet clocking in a single IC.
The clocks eliminate the need for multiple clock devices and voltage-controlled crystal oscillators (VCXOs) in demanding applications including small cells, distributed antenna systems (DAS), -BTS, baseband units (BBU) and fronthaul/backhaul equipment.
Over the next several years, service providers will lay the groundwork for 5G by deploying small cells, pico cells, DAS, µ-BTS and backhaul equipment that complements existing 4G/LTE networks by increasing outdoor network coverage and capacity and improving indoor signal reception.
As carriers transition to Ethernet-based eCPRI fronthaul networks to increase the capacity of fronthaul connections between base band units and remote radio heads, they are also deploying heterogeneous network (HetNet) equipment at the edge of the network where cost, power and size constraints present unique challenges for hardware designers.
The clocks are optimised to provide reference timing for HetNet equipment. Small cells and DAS equipment are “all-in-one” base stations that need reference timing for 4G/LTE transceivers, baseband processing and Ethernet/Wi-Fi connectivity.
The clocks replace a discrete clock IC, VCXO and loop filter components in a compact, single-chip design.
The clocks integrate five MultiSynth fractional clock synthesizers to provide simplified Ethernet and baseband reference timing. This streamlined, single-PLL design provides superior reliability to alternate solutions that rely on multiple PLLs and discrete oscillators.
Baseband units have complex timing requirements requiring multiple independent clock domains for CPRI or links to remote radio heads, Ethernet-based eCPRI for fronthaul networks and general-purpose clocks for local baseband processing.
The clocks support wireless frequencies up to 3 GHz with flexible any-rate DSPLLs optimized for Ethernet and general-purpose timing. Like the Si5386 clock, the Si5381/82 devices require no external VCXOs or crystals.
All PLL components are integrated on-chip in a space-saving 9 mm x 9 mm 64-LGA package. In addition, the clocks support a hitless switching capability that enables system designers to easily switch between different clock inputs and minimize phase transients, ensuring downstream PLLs remain in lock.
The devices are configurable and customizable using Silicon Labs’ flexible ClockBuilder Pro software.
Samples of the Si5381/82/86 wireless clocks are available now, and production quantities are planned to be available in December. Samples ship in two weeks, and production quantities are available in four weeks.
